The invention relates to a configuration having a trench capacitor and to a corresponding method of producing the configuration.
Integrated circuits (ICs) or chips use capacitors for the purpose of storing charges, such as a dynamic read/write memory with random access (DRAM). In this case, the charging state in the capacitor represents a data bit.
A DRAM chip contains a matrix of memory cells, which are provided in the form of rows and columns and are activated by word lines and bit lines. Reading data out of the memory cells, or writing data into the memory cells, is brought about by activating suitable word lines and bit lines.
A DRAM memory cell usually contains a transistor connected to a capacitor. The transistor contains two diffusion regions which are separated from each other by a channel which is controlled by a gate. Depending on the direction of the current flow, one diffusion region is referred to as the drain and the other as the source. The drain region is connected to the bit line, the source region is connected to the trench capacitor, and the gate is connected to the word line. By applying suitable voltages to the gate, the transistor is controlled in such a way that a current flow between the drain region and the source region through the channel is switched on and off.
The charge stored in the capacitor decays over time because of leakage currents. Before the charge has decayed to an indeterminate level below a threshold value, the storage capacitor must be refreshed. For this reason, these memory cells are referred to as dynamic RAM (DRAM). U.S. Pat. No. 5,867,420 discloses such a DRAM.
The central problem in the case of the known DRAM variants is the production of a sufficiently high capacitance in the trench capacitor. This problem will be intensified in the future as a result of the progressive miniaturization of semiconductor components. The continuous increase in the integration density means that the area available for each memory cell, and therefore the capacitance of the trench capacitor, will decrease more and more. Too low a capacitance of the trench capacitor can influence the functional capacity and usability of the memory device, since too low a quantity of charge is stored on it.
For example, read amplifiers need an adequate signal level to read out reliably the information stored in the memory cell. The ratio between the storage capacitance and the bit-line capacitance is decisive when determining the signal level. If the storage capacitance is too small, this relationship may be too small to produce an adequate signal.
Likewise, a low storage capacitance requires a higher refresh frequency, since the quantity of charge stored in the trench capacitor is limited by its capacitance and also decreases as a result of leakage currents. If the quantity of charge stored in the memory capacitor falls below a minimum, then it is no longer possible to read out the information stored in it by using the connected read amplifiers, the information is lost and read errors occur.
In order to avoid read errors, leakage currents should be low. On the one hand, leakage currents through transistors, and on the other hand leakage currents through dielectrics, such as the capacitor dielectric, can be reduced. Through the use of these measures, an undesirably reduced retention time can be prolonged.
In DRAMs, a trench capacitor is normally used. A trench capacitor has a three-dimensional structure, which is formed in a silicon substrate. An increase in the capacitor electrode area, and therefore in the capacitance of the trench capacitor, can be achieved by etching more deeply into the substrate. In this case, the increase in the capacitance of the trench capacitor does not enlarge the substrate surface taken up by the memory cell. However, this method is also restricted, since the achievable etching depth of the trench capacitor depends on the trench diameter, and only specific, finite aspect ratios can be achieved during production.
Given a progressive increase in the integration density, the substrate surface available for each memory cell decreases more and more. The associated reduction in the trench diameter necessarily leads to a reduction in the capacitance of the trench capacitor. If the capacitance of the trench capacitor is so low that the charge which can be stored is not adequate to be read out satisfactorily with the read amplifiers connected downstream, this results in read errors.
U.S. Pat. No. 5,360,758 discloses that in the case of memory cells with a trench capacitor and a transistor, a minimum spacing between the trench capacitor and the transistor must be maintained. This is required since, if there are temperature steps, the electrical contact between the trench capacitor and the transistor is produced by outward diffusion of a dopant, which is originally located in the trench capacitor. The outward diffusion of the dopant typically extends over distances which are greater than 100 nanometers. In this case, it must be ensured that the dopant does not diffuse into the channel of the transistor and consequently lead to increased leakage currents through the transistor and make the relevant memory cell unusable. This means that a memory cell which is theoretically possible without outward diffusion has to be enlarged by the magnitude of the outward diffusion.
It is accordingly an object of the invention to provide a trench capacitor configuration and a method of producing it which overcome the above-mentioned disadvantages of the heretofore-known configurations and methods of this general type and which provide an increased capacitance of the trench capacitor while maintaining the surface of the substrate, which is used by a memory cell, constant.
With the foregoing and other objects in view there is provided, in accordance with the invention, a trench capacitor configuration, including:
a substrate formed with a trench;
the trench having an upper region and a lower region;
an insulating collar formed in the upper region;
a buried well disposed in the substrate, the lower region at least partly extending through the buried well;
a buried plate formed around the lower region and serving as an outer capacitor electrode;
a dielectric layer lining the lower region and the insulating collar, the dielectric layer serving as a capacitor dielectric;
a conductive trench filling disposed in the trench; and
a conductive contact layer including at least one material selected from tungsten nitride, titanium nitride, and tantalum nitride, the conductive contact layer being disposed, between the substrate and the conductive trench filling, in the trench above the insulating collar.
The present invention is based on the idea of enlarging the trench 108 in the direction of the transistor 110 whilst keeping the substrate surface, which is used by the memory cell 100, constant. As a result, the proportion of the trench capacitor 160 on the substrate surface used is increased, and its capacitance increases. This is made possible by using a conductive contact layer 420, which serves as a diffusion barrier. In conventional trench capacitors, this diffusion barrier is not produced from tungsten nitride, and the electrical connection between the trench capacitor 160 and the transistor 110 is produced by the outward diffusion of dopants from a conductive trench filling 161 in order to form a buried contact 250. The diffusion barrier prevents the outward diffusion of materials, such as dopants or metals, which are contained in the trench filling 161 into the substrate 101, so that the transistor 110 is protected against the materials from the conductive trench filling 161 and maintains its advantageous characteristics. In this case, the connection between the trench capacitor and the transistor is produced by the conductive contact layer 420. The conductive contact layer 420 ensures a low-resistance connection to the conductive trench filling 161 and to the source region 114 and/or to an additionally introduced, buried contact 250. As a result, the spacing between the trench capacitor and the transistor can be reduced. In addition, while maintaining the lithographic dimension and the substrate surface used by the memory cell, the trench capacitor can be enlarged in the direction of the transistor.
A preferred embodiment of the invention provides for the conductive contact layer 420 to be provided in the trench 108 as a buried web on a side wall of the trench 108.
In an advantageous embodiment of the invention, there is in the trench 108, above the conductive trench filling 161, a buried bridge 162, which permits improved process control during the production of the buried contact 250, since by sinking the conductive trench filling 161, using an etching process with end-point monitoring, the sinking depth can be determined better. In this embodiment, the sunk, conductive trench filling 161, together with the buried bridge 162, constitutes the conductive trench filling.
In a further advantageous embodiment of the invention, a transistor 110 with a source region 114 is provided beside the trench capacitor, and the source region 114 reaches as far as the conductive contact layer 420. As a result, a low-resistance connection between the transistor 110 and the conductive contact layer 420, and hence the conductive trench filling 161 or the buried bridge 162 is achieved.
In a further advantageous embodiment of the invention, there is in the substrate 101, underneath a substrate surface 400, the buried contact 250, which reaches as far as the conductive contact layer 420, so that the buried contact 250 advantageously connects the buried bridge 162 and the trench filling 161 electrically to the source region 114 of the transistor 110. In order to form the buried contact 250, a dopant material can be introduced through the use of vertical or oblique implantation, through the use of plasma doping or through the use of gas-phase doping, through the substrate surface 400.
In a further advantageous embodiment of the invention, an additional lateral insulating web 410 is fitted to a side wall of the gate of a transistor, in order to protect the transistor from the dopant which is used to form the buried contact 250.
In a further advantageous embodiment of the invention, the conductive contact layer 420 is a diffusion barrier for a material which is contained in the conductive trench filling 161 and/or in the conductive buried bridge 162. As a result, the transistor 110 is protected against materials which can have a negative influence on its function.
According to another feature of the invention, the conductive contact layer 420 produces an electrically conductive connection between the buried contact 250 or the source region 114 and the conductive trench filling 161 or the conductive buried bridge 162.
In a further advantageous embodiment of the invention, a trench insulator 180 (STI), which has an insulating area 181, is applied in such a way that the trench 108 is at least partly covered by the insulating area 181. As a result, the passing word line 120xe2x80x2 is insulated from the conductive buried bridge 162 or, respectively, the conductive trench filling 161 which forms the inner capacitor electrode.
A further advantageous embodiment of the invention provides for the conductive contact layer 420 to be made of tungsten nitride WN, titanium nitride TiN or tantalum nitride TaN. With the objects of the invention in view there is also provided, a method of producing a trench capacitor configuration, the method includes the steps of:
introducing a buried well into a substrate;
forming a trench with an upper region and a lower region in the substrate;
forming an insulating collar in the upper region;
forming, at the lower region, a buried plate in the substrate for providing an outer capacitor electrode;
lining the lower region and an inner side of the insulating collar with a dielectric layer for providing a capacitor dielectric;
filling the trench with a conductive trench filling for providing an inner capacitor electrode; and
forming a conductive contact layer of tungsten nitride above the insulating collar.
In accordance with another mode of the invention, the conductive contact layer is formed on a side wall of the trench.
In accordance with yet another mode of the invention, a covering layer is applied onto the conductive contact layer.
In accordance with a further mode of the invention, a conductive buried bridge is formed in the trench above the conductive trench filling, such that the conductive buried bridge forms an electrical contact between the conductive trench filling and the conductive contact layer.
In accordance with another mode of the invention, a transistor is provided adjacent to the trench and a lateral insulating web is formed on a gate of the transistor.
In accordance with yet another mode of the invention, a dopant is introduced through a surface of the substrate.
In accordance with a further mode of the invention, a buried contact is formed with the step of introducing the dopant.
In accordance with another mode of the invention, a trench insulator with an insulating region is formed and a lower edge of the insulating region is provided above a lower boundary of the buried contact.
In accordance with a further mode of the invention, the insulating collar and the dielectric layer are removed in the upper region of the trench between the substrate and the conductive trench filling for forming an annular trench region; and the annular trench region is filled with the conductive contact layer.
In accordance with another mode of the invention, the conductive trench filling, the insulating collar and the dielectric layer are at least partially removed, in other words they are sunk into the trench, for exposing the substrate on a side wall of the trench; and the conductive contact layer is formed as a lateral edge web on the side wall of the trench by using a conformal layer deposition step and a subsequent etch-back step.
In accordance with yet another mode of the invention, a covering layer is conformally deposited on the contact layer prior to the etch-back step; and the contact layer with a broadened base at a lower end thereof is formed during the etch-back step.
An advantageous embodiment of the production method forms a trench insulator 180 with an insulating area 181, the lower edge 182 of the insulating area 181 being formed above the lower limit 251 of the buried contact 250.
A further advantageous embodiment of the method according to the invention forms a lateral insulating web 410 on a gate 112. The lateral insulating web 410 serves as a mask for the introduction of dopant through the substrate surface 400, whereby a buried contact 250 is formed.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a configuration having a trench capacitor, and a method for its production, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.